From e6383947713cd95bf212aec1d2afca59998ccf70 Mon Sep 17 00:00:00 2001 From: "kaf24@firebug.cl.cam.ac.uk" Date: Wed, 8 Mar 2006 11:53:39 +0100 Subject: [PATCH] The PAE guest can run on SMP 64-bit Xen0 now. Optimize the save/restore action for EFER MSR during the context switch. Signed-off-by: Jun Nakajima jun.nakajima@intel.com Signed-off-by: Xiaohui Xin xiaohui.xin@intel.com Signed-off-by: Yunhong Jiang --- xen/arch/x86/hvm/vmx/vmx.c | 16 ++++++---------- xen/arch/x86/shadow.c | 5 +++++ xen/include/asm-x86/shadow_64.h | 5 ++++- 3 files changed, 15 insertions(+), 11 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 18d532a61b..05a099e2c1 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -223,6 +223,11 @@ static inline int long_mode_do_msr_write(struct cpu_user_regs *regs) switch (regs->ecx){ case MSR_EFER: + /* offending reserved bit will cause #GP */ + if ( msr_content & + ~( EFER_LME | EFER_LMA | EFER_NX | EFER_SCE ) ) + vmx_inject_exception(vc, TRAP_gp_fault, 0); + if ((msr_content & EFER_LME) ^ test_bit(VMX_CPU_STATE_LME_ENABLED, &vc->arch.hvm_vmx.cpu_state)){ @@ -236,18 +241,9 @@ static inline int long_mode_do_msr_write(struct cpu_user_regs *regs) if (msr_content & EFER_LME) set_bit(VMX_CPU_STATE_LME_ENABLED, &vc->arch.hvm_vmx.cpu_state); - /* No update for LME/LMA since it have no effect */ + msr->msr_items[VMX_INDEX_MSR_EFER] = msr_content; - if (msr_content & ~(EFER_LME | EFER_LMA)){ - msr->msr_items[VMX_INDEX_MSR_EFER] = msr_content; - if (!test_bit(VMX_INDEX_MSR_EFER, &msr->flags)){ - rdmsrl(MSR_EFER, - host_state->msr_items[VMX_INDEX_MSR_EFER]); - set_bit(VMX_INDEX_MSR_EFER, &host_state->flags); - set_bit(VMX_INDEX_MSR_EFER, &msr->flags); - } - } break; case MSR_FS_BASE: diff --git a/xen/arch/x86/shadow.c b/xen/arch/x86/shadow.c index 6ed126eb96..f34653d95d 100644 --- a/xen/arch/x86/shadow.c +++ b/xen/arch/x86/shadow.c @@ -3583,6 +3583,11 @@ static inline int guest_page_fault( ASSERT( d->arch.ops->guest_paging_levels >= PAGING_L3 ); +#if CONFIG_PAGING_LEVELS >= 4 + if ( (error_code & (ERROR_I | ERROR_P)) == (ERROR_I | ERROR_P) ) + return 1; +#endif + #if CONFIG_PAGING_LEVELS == 4 if ( d->arch.ops->guest_paging_levels == PAGING_L4 ) { diff --git a/xen/include/asm-x86/shadow_64.h b/xen/include/asm-x86/shadow_64.h index 237adb3e84..b0d755d39a 100644 --- a/xen/include/asm-x86/shadow_64.h +++ b/xen/include/asm-x86/shadow_64.h @@ -51,8 +51,11 @@ typedef struct { intpte_t l4; } l4_pgentry_t; #define READ_FAULT 0 #define WRITE_FAULT 1 -#define ERROR_W 2 +#define ERROR_P 1 +#define ERROR_W 2 #define ERROR_U 4 +#define ERROR_I (1 << 4) + #define X86_64_SHADOW_DEBUG 0 #if X86_64_SHADOW_DEBUG -- 2.30.2